1. Field of the Invention
The present invention relates to synchronous memory, and in particular to a synchronous memory that can dynamically enable address receivers.
2. Description of the Prior Art
Synchronous memory has simpler timing requirements than asynchronous memory, which has to generate a pulse every time a write operation occurs. Synchronous memory has signals that operate on clock edges, and therefore can operate at a much faster frequency than asynchronous memory. In a multiple bank memory with a shared address scheme, such as a Double Data Rate-4 (DDR4) memory, address signals input to a specific bank can produce a transient current to other banks A conventional method therefore introduces decoding logic to selectively latch or release addresses to an internal address bus.
Please refer to FIG. 1, which is a diagram of a synchronous memory 100 according to the prior art. As can be seen from the diagram, the synchronous memory 100 has a clock receiver 130 for receiving a clock signal, a command receiver 120 for receiving a command signal (CMD1, CMD2, CMD3 etc.) and an address receiver 110 for receiving an address signal (ADD1, ADD2, ADD3 etc.). Only one set of receivers is shown here for simplicity. As can be seen from the timing diagram in FIG. 1, the command signal and address signal are received by the command receiver 120 and the address receiver 110 respectively in a same clock cycle. The command signal is decoded utilizing the aforementioned decoding logic to generate a command clock CMD_CLK for latching or releasing the address signal to the internal address bus. The address signal will first be buffered in the buffer 152 before being released to the internal address bus.
As the address signal and command signal are received in the same clock cycle, the address receivers need to be permanently ‘on’. This consumes considerable power. Therefore, providing a system for selectively turning on address receivers when they are required to be operational is desired.